Re: [openoffice] branch AOO418 updated: Fix broken compile for older Linux... disable HW accel just as we used to do before

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Re: [openoffice] branch AOO418 updated: Fix broken compile for older Linux... disable HW accel just as we used to do before

Don Lewis-2
On  6 Oct, [hidden email] wrote:
> This is an automated email from the ASF dual-hosted git repository.
>
> jim pushed a commit to branch AOO418
> in repository https://gitbox.apache.org/repos/asf/openoffice.git
>
>
> The following commit(s) were added to refs/heads/AOO418 by this push:
>      new 0a99449  Fix broken compile for older Linux... disable HW accel just as we used to do before
> 0a99449 is described below

This is a bit misleading.  The code compiles fine and works properly on
CentOS 5.  It just won't run on older hardware that doesn't have the new
crypto instructions.  I didn't catch it since I built and tested the
code on a CentOS 5 VM running on a Ryzen.

Good catch.  The next nss upgrade probably has the same problem.

> commit 0a994498bd0b70dfacbfd49f6470cce09e547165
> Author: Jim Jagielski <[hidden email]>
> AuthorDate: Tue Oct 6 15:42:08 2020 -0400
>
>     Fix broken compile for older Linux... disable HW accel just as we used to do before
> ---
>  main/nss/nss_linux.patch | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
>
> diff --git a/main/nss/nss_linux.patch b/main/nss/nss_linux.patch
> index 9d768b2..50c27a4 100644
> --- a/main/nss/nss_linux.patch
> +++ b/main/nss/nss_linux.patch
> @@ -12,3 +12,18 @@ diff -ur misc/nss-3.25/nss/lib/freebl/Makefile misc/build/nss-3.25/nss/lib/freeb
>   EXTRA_SRCS += intel-gcm-wrap.c
>   ifeq ($(CLANG_CL),1)
>      INTEL_GCM_CLANG_CL = 1
> +@@ -221,10 +221,10 @@
> +     DEFINES += -DMP_IS_LITTLE_ENDIAN
> + #   DEFINES += -DMPI_AMD64_ADD
> +     # comment the next four lines to turn off Intel HW acceleration.
> +-    DEFINES += -DUSE_HW_AES -DINTEL_GCM
> +-    ASFILES += intel-aes.s intel-gcm.s
> +-    EXTRA_SRCS += intel-gcm-wrap.c
> +-    INTEL_GCM = 1
> ++    #DEFINES += -DUSE_HW_AES -DINTEL_GCM
> ++    #ASFILES += intel-aes.s intel-gcm.s
> ++    #EXTRA_SRCS += intel-gcm-wrap.c
> ++    #INTEL_GCM = 1
> +     MPI_SRCS += mpi_amd64.c mp_comba.c
> + endif
> + ifeq ($(CPU_ARCH),x86)
>


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